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    PG Diploma in VLSI design

    Module -1:VLSI concepts and core fundamentals(1 week)

    VLSI - Why, What, How, Who and When-Lecture Sessions

    VLSI – Digital, Analog and Mixed-signal

    VLSI – fundamentals at MOS level

    VLSI – fundamentals at Gate level

    VLSI – fundamentals at IC level

    Module-2: VLSI design flow for ASICs and FPGAs(2 weeks)

    VLSI design flow – design, CAD tools

    Simulation and synthesis

    High level design aspects –  Digital systems

    Timing issues and high speed circuit design techniques

    CMOS design issues

    CMOS variants for high performance

    Delay models (inertial and transport)

    Nano meter IC design –  key challenges and trends

    Common abstraction for FPGA and ASIC design

    Digital design exercises-1,2,3,4 (homework and classroom discussion)

    Lecture sessions

    Design Exercises

    Module -3 Designing with VHDL (3 weeks)

    Concept behind HDLs

    VHDL syntax rules

    Operators and attributes

    VHDL as object oriented approach – data types

    Digital Hardware to VHDL constructs mapping

    Simulation and synthesis aspects

    RTL coding fundamentals

    Controlled data path design

    State machine coding and optimization issues

    Steps in VHDL based IC design flow (specification to layout)

    Xilinx design flow with ISE tools

    Functional simulation

    Timing simulation

    Applying area and timing constraints

    Xilinx FPGA architecture basics

    Writing test benches (simple, file based, scripts)

    Miniproject-1 (Digital design, VHDL coding, testing on Xilinx FPGA board)

    Lecture sessions

    Lab sessions


    Module-4 Designing with Verilog

    Bridging from VHDL to Verilog

    Key syntax issues and similarity with C

    Operators in Verilog

    Verilog identifiers, code constructs

    Blocking and Non-blocking code

    Combinational circuits with verilog

    Sequential blocks with verilog

    RTL coding for efficient synthesis in Verilog

    Verification in Verilog

    Scripting for system level verification in Verilog – Interface to other languages

    Lecture sessions

    Lab sessions


    Module-5 Advanced course on complex FPGA design (2 weeks)

    Basics of Xilinx and Altera FPGA architectures

    Fuse & Antifuse FPGA architectures
    (ACTELandLattice semiconductor)

    Modern Xilinx FPGAs –  6 and 7 family

    Key components - DSP48s, DCMs, BRAMs, IOBs

    High speed complex system design with Virtex-6 and 7 FPGAs

    Implementing control logic on FPGAs

    Implementing DSP on FPGAs

    High speed communication- DDR interfaces, SRIOs

    Key board design fundamentals for FPGAs

    Case study - complex FPGA based system

    Lecture sessions

    Lab sessions on new generation Xilinx FPGAs

    Case study

    Module-6 ASIC – design, synthesis and timing aspects (2 weeks)

    ASIC EDA tools

    Synthesis issues and constraints

    Clock routing aspects and optimization

    Critical path analysis (false paths , multi cycle paths)

    Schematic entry and ASIC simulation

    Timing aspects and power analysis

    Layout entry for CMOS designs

    DRC for CMOS submicron and nanometer technologies

    LVS for CMOS based designs (130 nm examples)

    Understanding the process models and model files

    Power analysis for complex ASIC designs

    Low power design techniques –  An overview

    Miniproject (schematic, layout, DRC, LVC, simulation, timing and power analysis)

    Lecture sessions

    Lab sessions


    Module-7 SOC testing - Verification and Validation (2 weeks)

    Modern SOC verification challenges

    Testing Vs Verification

    Yield analysis in nano meter ICs

    Fault modeling in SOCs and simulation

    Fault tolerance methods

    Design for testability (DFT)

    BDD and TPG

    Bound scan chain

    Test pattern generators


    Faults in memory chips

    March testing

    Introduction to Formal Verification

    linear temporal logic (LTL) and computational tree logic (CTL)

    Lecture sessions

    Lab sessions

    Project work-2